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Intel outlines its struggles with 10-nm chip production

Hillsboro, we have a problem

On Intel's most recent earnings call, CEO Brian Krzanich finally admitted what many in the industry have long intuited, understood, or scooped: the company is struggling with its 10-nm process technology, and those struggles are preventing the company from achieving good yields of 10-nm chips.

Krzanich admitted to analysts that the company "bit off a little too much" with its aggressive 2.7x scaling target for the process compared to its 14-nm products. Consequently, Intel says it's in the process of correcting the yield issues it has identified with its chips. The downside is that those yield issues will apparently require lots of time yet to resolve. Although Krzanich still says Intel is shipping 10-nm products today (although it still isn't clear to whom), the CEO says volume production of 10-nm silicon will not occur before 2019, and he wouldn't confirm to analysts whether that production would occur in the first half or second half of that year.

Area trends in Intel process technologies. Source: Intel

As a result, we could be waiting anywhere from six to 18 months for 10-nm silicon to appear in volume—a window that is sure to be deeply unsettling to the company's manufacturing partners and investors given that 10-nm products have been experiencing delays since 2015, at least.

Krzanich plainly stated that 10-nm yield woes are because of the company's implementation choices for its next-gen process tech. Intel's 10-nm process is rather unusual among cutting-edge lithography because of the company's decision to forgo EUV insertion entirely in favor of multi-patterning with traditional 193-nm deep ultraviolet light sources.

Although Intel has said in the past that it was using self-aligned quad patterning as part of 10-nm production, Krzanich offered the eyebrow-raising prospect that the company has to employ as many as five or six multi-patterning steps to create certain 10-nm features in response to one analyst question.

Krzanich didn't say whether those figures were merely examples of multi-patterning in general or specific examples of steps needed to produce Intel 10-nm chips, but the sheer number of steps inolved in multi-patterning on that scale could be a major factor in the yield problems that Intel is experiencing. As GlobalFoundries put it to me during our foundry tour earlier this year, every interaction a silicon wafer has with lithography tools increases the chance of a defect, and multi-patterning involves a lot of interactions with those tools as a wafer is shepherded to completion.

In contrast, GlobalFoundries notes that EUV not only allows for more efficient usage of foundry capacity, it also reduces the number of times equipment needs to interact with the wafer. EUV users still face significant challenges of their own regarding yields and defect detection in the masks that will be used to guide light to wafers, but the fact that it broadly reduces the number of steps involved in putting chips on silicon may have positive implications for yields and productivity, all else being equal.

Intel won't enjoy any of the potential benefits of EUV before its 7-nm process goes into production. Krzanich told analysts that 10-nm will be the last Intel lithography node without EUV insertion, but the company hasn't announced a timeline for insertion of those tools or when it'll begin high-volume 7-nm manufacturing. Given the lengthy continued work that 10-nm appears to need before it enters high-volume manufacturing, it's not at all clear when Intel 7-nm chips will first see the light of day.

The toil on 10-nm appears necessary for transitions to future nodes, as well. Krzanich told analysts that the company plans to stay the course on 10-nm so that it can glean the knowledge it needs to effectively make 7-nm silicon, rather than throw away the work it's already invested in 10-nm production and jump straight to the next process node.

Even with the delays involved in ironing out yield issues, the 10-nm silicon slated to arrive in 2019 will still be of the first-generation variety—not the "10-nm+" transistors that seem poised to finally outperform those available from the ultimate n-plus variants of the evergreen 14-nm process. The CEO told analysts that the improvements going into 10-nm at the moment are mostly focused on yield improvements for the base process, not the performance gains offered by a 10-nm+ variant.