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Ice Lake freezes over

Although nobody would explicitly say so at the event, Intel has essentially halted any volume-production plans it might have had for the Cannon Lake microarchitecture introduced with the Core i3-8121U. The first next-generation core built on the 10-nm process that Intel is confident enough to talk about in detail is called Sunny Cove, a name that refers only to the CPU core and not the SoCs that the company plans to build around it. That said, and despite some taciturn responses to questioning on this point at the event, I'm confident in saying that the first 10-nm processors that Intel plans to introduce in volume will fly the Ice Lake code name.

Sunny Cove is the first in the company's revised 10-nm roadmap, and it'll presumably begin arriving in client systems starting in the second half of 2019. To be clear, the "Cove" suffix refers to the CPU core inside Ice Lake, not the entire SoC itself. The company's core roadmap also includes Willow Cove, whose highlights may include a cache redesign, a "new transistor optimization," and enhanced security features. The Golden Cove follow-in in the 2021 time frame returns the focus to single-threaded performance, AI performance, networking and 5G performance, and more security enhancements.

Intel-watchers have long desired better fundamental per-core performance for some time, and Sunny Cove appears positioned to deliver. Intel's Ronak Singal noted that the best way to extract general-purpose performance improvements from a CPU is to make it deeper (by finding greater opportunities for parallelism), wider (by making it possible to execute more operations in parallel), and smarter (by introducing newer and better algorithms to reduce latency).

Sunny Cove goes deeper by expanding its caches and record-keeping infrastructure to keep more instructions and data near the coreĀ and in flight. This core moves from a 32-KB L1 data cache to a 48-KB allocation. The L2 cache per core will increase, although as we've seen in the divergence between Skylake client and server cores, the amount of L2 will differ by product. The micro-op cache also increases in size, and the second-level translation lookaside buffer (TLB) is also more copious than in Skylake.

Sunny Cove is a fundamentally wider core than most every Intel design since Sandy Bridge, as well, expanding from four-wide issue to five-wide and increasing the number of execution ports from eight to 10. Each of those execution units, in turn, is more capable than those of Skylake. Intel added a dedicated integer divider on port 1 to reduce latency for those operations.

The core now has two pathways for storing data, and it now has four address-generation units (up from three in Skylake). The vector side of the chip now has two shuffle units (up from one in Skylake), and every one of the four main execution ports can now perform a load effective address (LEA) operation, up from two such units in Skylake. Sunny Cove also implements support for the AVX-512 instruction set extension that was first meant to be introduced to client systems by way of Cannon Lake.


An early Ice Lake-SP package.

To bolster the idea that Intel's 10-nm process is in a healthier place than it has been of late, we saw at least three separate implementations of Sunny Cove cores running: at least one development board using an Ice Lake-U processor, another development board featuring Intel's Foveros 3D packaging technique (more on that later), and an Ice Lake-SP Xeon demonstrating new extensions to the AVX-512 instruction set. While the company certainly wasn't ready to talk exact die sizes, it was heartening to see 10-nm silicon ranging from minuscule to massive in operation.