Despite this handicap, the single-barreled shotguns performed wellespecially the PT800, whose spunky performance (with one DIMM installed, at least) surprised us. VIA and SiS were coming close to catching Intel.
Now comes the encore. Both VIA and SiS have prepped their dual-channel memory controllers, and both chipsets are now at rough feature parity with Intel. The Intel competition hasn't sat still, however. Last time around, we used Intel's own typically tame motherboards to test the 865PE and 875P chipsets. This time out, we're using Abit's spicy IC7-G, a tricked-out enthusiast's mobo with playing-for-keeps performance. And we've cut out the stock 865PE chipset, because all the decent enthusiast's boards these days have BIOS options that enable internal memory controller timings entirely similar to the 875P's Performance Acceleration Technology (PAT), erasing the most notable distinction between the 865PE and 875P.
To make things even more interesting, we've blindsided our contestants with a series of I/O and south bridge tests, measuring everything from USB 2.0 transfer rates to Ethernet performance and CPU overhead.
Are Taiwan's "twin dragons" finally ready to take on the chipsets Intel launched back in April? Well, only one way to find out...
SiS goes Hyper: the 655FX
SiS beat VIA to the punch by a little bit with the 655FX, no doubt in part due to the fact that SiS already had, in the form of the 655 north bridge, a dual-channel memory controller ready to be tweaked into supporting DDR400 memory speeds. SiS, however, didn't have a south bridge with an integrated Serial ATA controller ready to roll until more recently. The 648FX reference board we tested had a discrete SATA controller hanging off the PCI bus, but it hadn't made the leap to the south bridge. Now, the 655FX north bridge can team up with the 964 south bridge to deliver two Serial ATA ports and support for RAID levels 0, 1, and Just a Bunch Of Disks (JBOD, for shortin this case, just a pair of disks). All told, the 655FX north bridge and 964 south bridge bring SiS up to snuff, feature-wise, versus the competition.
Little SiS has a couple other tricks up her sleeve, as well. One is an extra-flexible memory controller, and the other is HyperStreaming.
Hang on. Let's talk memory controllers first. Believe it or not, most north bridge dual-channel memory controllers aren't wildly sophisticated in how they go about their work. There are no fancy crossbars with load-balancing algorithms like you'd find in a GPU memory controller. Instead, the 875P, PT880, and 655FX all deliver "dual-channel" functionality by addressing a pair of memory banks as one, single 128-bit memory bank. It isn't an exotic, SGI-inspired method, but it works. Consequently, today's dual-channel chipsets typically require DIMMs to be installed in identical pairs, or they'll drop back into single-channel mode, losing the magic.
The 655FX can operate in the typical 128-bit mode, but it can also run in a "concurrent" dual 64-bit mode when DIMM pairs don't match. One could, for instance, configure a 655FX system with three 256MB DIMMs, for a total of 768MB, and still get the benefits of a dual-channel memory controller. The 655FX north bridge automatically configures itself based on the DIMMs installed. When possible, the 128-bit mode is still the preferred option for best performance.
Now, about that Hyper. SiS is making a big push for its HyperStreaming Architecture. I've studied the marketing materials, and near as I can tell, the HyperStreaming Architecture is, erm, well, SiS's core-logic chipset architecture. I could be wrong. Last time I wrote about HyperStreaming, I decided it was just another term for SiS's MuTIOL, or Multihreaded I/O Link, between the north and south bridge chips. However, this slide would suggest I was wrong:
HyperStreaming apparently encompasses the entire chipset design, and includes the AGP, front-side bus, and memory interfaces. What's more, the primary locus of HyperStreaming's key features is the apparently north bridge chip, not the south bridge. I believe what SiS is trying to tell us is that its engineers applied certain key principlessmart bus arbitration, pipelining, split transactions, and parallelismas needed in designing the latest SiS core-logic chips. The goal was to facilitate the uninterrupted movement of data streams through the system, from an I/O controller into main memory, say, with low latency and adequate bandwidth. This is, after all, what core-logic chipsets do.
Lo and behold, we will be measuring just such things in our testing, so we'll see how well SiS's Hyper stands up to the non-Hyper competition.
I can tell you one Hyper that didn't Stream for us, and that's SiS's SATA controller. Unfortunately, the SATA controller on our 655FX reference board just didn't work right. Knowing how these things go with low-volume boards like reference samples, it's probably a one-off problem with the motherboard. SiS suggested we test a production 655FX board to see how well SATA works. Right now, however, availability of 655FX-based motherboards is still very limited (I see one listing on Pricewatch as I write this). So we had to stick with the reference board and live with an ATA/100 disk drive for our testing.