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Model number mania!
Since making the move to CPU model numbers, AMD has been abusing the convention by playing mix 'n' match with clock speeds, cache sizes, and the number of memory channels on a processor. It's possible to buy no less than four different varieties of Athlon 64 3200+, for example. This kind of marketing shell game may be confusing to the public, but it's an important esteem-building exercise for the marketing majors inhabiting an engineering-driven company.

Don't think Intel's marketing types aren't salivating to crank up the model number madness themselves. In fact, rather than replace it, the Pentium 4 600 series will coexist with the 500 series for the time being.

But I'm oversimplifying. You see, the 500 series is already being replaced by the 500J series, which includes Execute Disable Bit and C1E halt state support, but not EM64T or SpeedStep.

So the 600 series will coexist with the 500J series, you see.

What about pricing, you ask? Well, in order to make it plain as day, I've laid out the list prices for the various AMD and Intel desktop processors in a table. Here's how it looks.

Pentium 4 ModelClock speed (GHz)List PricePentium 4 ModelClock speed (GHz)List priceAthlon 64 ModelList price
520J2.8$163   3000+$149
530J3.0$178   3200+$194
There you have it. Now, when a confused, non-techie friend asks you which Pentium 4 processor he should buy, you have the information to answer confidently, "I have no idea." You may optionally lapse into extended explanations of clock speed versus cache size, EM64T versus 32 bits, C1E halt state versus SpeedStep, and all the rest, but Intel has already done the hard work for you by pricing the two product lines nearly on top of each other.

To be fair, I think the obvious choice for those in the know will be the 600 series, given its EM64T support. Intel has said that it plans to extend EM64T capability across its desktop line, from the top all the way down to the Celeron D, eventually. That's apparently not going to happen until later this year, though. Other considerations in the 500-vs.-600-series debate, including performance and power management, are quite a bit more complicated than one might expect.

Sorting out the various types of power management
One of the potentially most compelling features of the new P4 600 series is its support for Enhanced SpeedStep power management. By ramping down the processor's clock speed and voltage when there's little work to be done, SpeedStep should help alleviate the Pentium 4's power and heat problems. It should also allow for much quieter Pentium 4 systems, at least at idle. However, SpeedStep alone is only part of the picture. The newer Pentium 4 processors use the same transistors on the chip in order to implement three different power and heat management functions that are distinct, but fundamentally similar. All three functions dynamically adjust the processor's clock speed and voltage. They are:

  • C1E enhanced halt state — Introduced in the Pentium 4 500J-series processors, the C1E halt state replaces the old C1 halt state used on the Pentium 4 and most other x86 CPUs. The C1 halt state is invoked when the operating system's idle process issues a HLT command. (Windows does this constantly when not under a full load.) Entering halt state, which is a lower-power state, will cut a CPU's power consumption and heat production. Intel's new C1E halt state is also invoked by the HLT command, but it turns down the entire CPU's clock frequency (via multiplier control) and voltage in order to work its mojo. This more robust halt state requires significantly less power than the old C1 implementation.

    C1E halt cranks the CPU bus multiplier down to its lowest possible level on the 600-series processors, which is 14X, so a P4 660 processor with the C1E halt state active actually runs at 2.8GHz. I believe that C1E halt is also a binary condition invoked by the HLT command; it's either on or it's off.

  • Enhanced SpeedStep — SpeedStep also modulates the CPU clock speed and voltage according to load, but it is invoked via another mechanism. The operating system must be aware of SpeedStep, as must the system BIOS, and then the OS can request frequency changes via ACPI. SpeedStep is more granular than C1E halt, because it offers multiple rungs up and down the ladder between the maximum and minimum CPU multiplier and voltage levels.

    Intel cites its mobile products when talking about SpeedStep, which is apt but not entirely helpful because it conjures up images of the Pentium M processor, a very different beast. The Pentium 4 doesn't contain most of the heroic power-saving measures of the Pentium M.

  • TM2 thermal throttling — Since the beginning, all Pentium 4 processors have included a facility for throttling themselves back in the event that they should begin to overheat. This facility, called Thermal Monitoring 1 or TM1, essentially tells the Pentium 4 to take half its clock cycles off, cooling the CPU and reducing power by about 50%. Externally, the chip still runs at its rated frequency, but internally, it runs at half that. This throttling mechanism is effective, but it has several disadvantages. As Michael Schuette has noted, the rest of the system doesn't know what to do with an internally throttling Pentium 4, and the memory subsystem can be thrown into a retry loop that causes it to heat up. For the same reason, TM1 throttling can really harm performance.

    TM2 throttling instead steps down CPU voltage and clock speed via the same mechanism as C1E and SpeedStep, effectively cooling the CPU by roughly 40% without affecting performance as severely TM1 throttling does. TM2 shouldn't throw the memory subsystem into a retry loop, either. Like TM1 throttling, TM2 becomes active when the CPU decides it's getting too hot.

Obviously, the practical difference between TM2 throttling and the other two functions is easily discernible. The practical difference between C1E halt and SpeedStep, however, is more difficult to pinpoint and is literally quite marginal. SpeedStep will adjust clock frequency and voltage more gradually during transitions between idle and busy times, but C1E would seem to accomplish more or less the same thing a little less gracefully. SpeedStep may opportunistically grab a little more power savings here and here on a partially loaded system, but I wouldn't expect dramatic differences. C1E's great advantage is that it's transparent to the operating system and requires no special support other than the already widely used HLT command.

Oddly, although these two functions use the same transistors, Intel has elected to endow the Pentium 500J series with C1E halt but not SpeedStep, while the 600 series gets both. This is apparently a product segmentation decision.

As I noted, this CPU core's lowest possible CPU bus multiplier is 14X, which explains why the new Extreme Edition 3.73GHz lacks C1E halt, SpeedStep, and TM2 support. Thanks to its 1066MHz front-side bus speed, the new EE runs at a 14X multiplier by default, and thus has no ability to turn down its clock speed. I have to think that, were Intel fully committed to making the P4 Extreme Edition a compelling product, they would have added some lower multipliers to the chip. Doing so probably wasn't worth the extra effort for such a low-volume product, though.