We still didn't get a roadmap update with product code names and target dates, but we did get a sense of what features AMD is planning to build into its CPUs in the coming months and years.
Given that this was the opening of Fab 36, the most immediate question on our mind was about the transition to 65nm process technology. Fab 36 will start by manufacturing 300mm wafers using 90nm process tech and then transition to 65nm some time in 2006. AMD wasn't especially specific about the time frame for that transition, but I believe they expect it to happen in the next six to nine months. As I understand it, the manufacturing equipment in place in Fab 36 is already capable of 65nm production. AMD's hope is to work the kinks out of the new fab, bring chip yields up to par at 90nm, and then transition rapidly to 65nm with a quick ramp to strong yields once again.
One slide to rule them all
So that's the story on 65nm. Most of the rest of what we learned was summarized in a single slide from Hester's presentation. It looked like so:
We'll begin with the "now" column, because it has a bit of a surprise in it: the mention of DDR2 support. Actually, DDR2 support isn't quite here yet, but it is coming. Next year, AMD will transition the Athlon 64 to a new 940-pin socket called Socket M2, and chips that slip into this socket will come with DDR2 support built into their integrated memory controllers. Like AMD's current socket designs, M2 will be a pin-based socket, so really not much changes. In fact, since the memory controller is built into the CPU, adding DDR2 support will not require a revised core-logic chipset. Beyond that one anomaly, the "now" column in the slide above should look pretty familiar.
The "coming soon" column is, obviously, more interesting, because there we see some new and different things. Hester said we should start seeing some items in this column in the next 12 months or so, roughly speaking.
First up on the list of things coming soon are some new extensions to the AMD64 instruction set. I would expect these to be performance-enhancing instructions aimed at specific types of tasks, much like the various SSE extensions are. Hester mentioned the possibility of accelerating 3D rendering with these extensions, but beyond that, their exact nature and use remains a mystery.
Next, the "multi-core" architecture line is distinct from dual cores because they're talking about the possibility of two, four, or eight cores per chip. Hester stressed the need for AMD to pay attention to the software ecosystem before moving ahead on adding additional cores for specific markets, especially in the desktop, where truly multi-threaded applications are still relatively scarce. I tried to tease out whether AMD would aim to deliver a quad-core processor on the 90nm fab process, but Hester wouldn't say.
I also asked him about the possibility of a three-core design for desktop processors. Given the fact that his presentation specifically mentioned two, four, and eight cores as part of AMD's future direction, I doubt that a three-core processor is coming any time soon. However, Hester noted that AMD's CPU architecture is highly modular, and said that there's nothing magic about powers of two that would lead them away from considering a three-core design. The question, he said, is simply whether the transistors for a third core might be better spent on something else, like a larger on-chip cache. Unfortunately, he offered no hint of AMD's take on the answer.
On the server front, more cores are very welcome, especially for high-end database applications and the like. To that end, the "Scalable SMP architecture" point refers to server systems coming from AMD partnerslikely tier 1 OEMswith as many as 32 sockets and thus 64 cores when used with dual-core Opterons. Such large systems would surely benefit from the already-announced Pacifica, the virtualization capability similar to Intel's Vanderpool Technology; this feature will help enable a single system to run multiple operating systems simultaneously. HyperTransport 3.0 has been reported to offer up to three times the speed of today's HyperTransport interconnects, and it might also be quite helpful in a 32-socket server.
Support for fully-buffered DIMMs and DDR3 isn't among the features in the "coming soon" column that I'd expect AMD to deliver, well, soon. The ability to handle these new memory types likely won't come until the JEDEC specifications are complete and the memory chips are well into production.
On the other hand, let's hope we see partitioned PowerNow! technology in the relatively near future. Also known as Cool'n'Quiet on desktop processors like the Athlon 64, PowerNow! dynamically scales CPU clock speeds and voltages in response to system load, reducing power consumption when the processor isn't busy. The partitioned version of PowerNow! will allow the individual cores on a multi-core processor to adjust their clock speeds and voltages independently.
As for the "mainframe-class reliability" point, I'm unsure whether that's related to a specific CPU architectural innovation or not. It may well just be a goal that AMD is pursuing with its partners, especially in conjunction with the development of 32-socket SMP systems.