Future goals: reconfigurable cores and system resource management
The bits mentioned in the "future goals" column are further out into the future and more nebulous, but some of them are potentially more exciting, as well. At the top of the list are FPU-oriented extensions to the AMD64 instruction set. I'm speculating a bit here, but these new extensions may go hand-in-hand with another eyebrow-raising item in the list, "on-chip coprocessors." At first blush, these words would seem to suggest the addition of some specialized cores on chip to handle specific types of math, but that's apparently not what AMD has planned. Instead, Hester said that beyond two cores, additional general-purpose cores on the chip could be thought of as configurable co-processors. The specialized FPU extensions to AMD64 may help in this regard, allowing for more flexible allocation of the execution resources on those cores. Hester mentioned two possible applications for reconfigured cores: 3D graphics and data encryption.
The ability to reconfigure cores for certain types of applications may tie in with the "system resource management" point, as well. Initially, I thought any talk of system resource management would naturally be referring to an AMD response to Intel's AMT initiative, but Hester said no, this is something different. AMD's system resource management involves OS-CPU communication about what sort of execution resources an application needs at a given time. Presumably, such information could be used to invoke the reconfiguration of one or more processor cores in order to meet the app's demands, and to help direct the dispatching of threads to those cores. Such a facility might also be used to enable a power-saving idea that AMD has mentioned a number of times: the use of a simple, low-power, x86-compatible processor core to handle basic system chores and spin off more intensive threads to beefier cores when needed.
Plans to conjure up new instruction set extensions tied to new processor capabilities are exactly what AMD needs to hang onto the reputation for leadership that it's earned during the Athlon 64/Opteron era, but such initiatives come at a price: the company will have to work with OS vendors to support these features, and it will have to win support from independent software vendors, as well. To that end, Hester said that AMD will be stepping up its software investments, so that compilers and applications will be available to take advantage of these new capabilities.
The only other bit in the "future goals" column that's really familiar is the "secure execution" feature, which I'd associate with AMD's Presidio initiative. Presidio has been called similar to Intel's LaGrande technology. Beyond that, most of the things listed here are future spec extensions like HyperTransport 4.0, DDR4 memory, and the second revision of fully-buffered DIMMs. I have no idea what "throughput architecture" is; it may simply be a marketing name for the combination of reconfigurable cores and dynamic resource management, or it may be something else entirely.
The making of new mobile mojo
We also asked a few questions about AMD's future mobile CPU efforts. Hester said that at some point, AMD will need an all-new processor core that's optimized for mobile use, and he confirmed that efforts are underway to make that happen. He couldn't say yet how much commonality there would be between this new mobile core and AMD's desktop processors, but he did say that the project's design points have already been set.
When asked about the possibility of AMD employing a CMOS voltage regulator like the one Intel touted at IDF, Hester was less than enthusiastic about the concept. He didn't strictly rule out the possibility of AMD adopting such technology at some point in the future, but he was pessimistic about the cost of such a device.