On Intel’s most recent earnings call, CEO Brian Krzanich finally admitted what many in the industry have long intuited, understood, or scooped: the company is struggling with its 10-nm process technology, and those struggles are preventing the company from achieving good yields of 10-nm chips.
Krzanich admitted to analysts that the company “bit off a little too much” with its aggressive 2.7x scaling target for the process compared to its 14-nm products. Consequently, Intel says it’s in the process of correcting the yield issues it has identified with its chips. The downside is that those yield issues will apparently require lots of time yet to resolve. Although Krzanich still says Intel is shipping 10-nm products today (although it still isn’t clear to whom), the CEO says volume production of 10-nm silicon will not occur before 2019, and he wouldn’t confirm to analysts whether that production would occur in the first half or second half of that year.
As a result, we could be waiting anywhere from six to 18 months for 10-nm silicon to appear in volume—a window that is sure to be deeply unsettling to the company’s manufacturing partners and investors given that 10-nm products have been experiencing delays since 2015, at least.
Krzanich plainly stated that 10-nm yield woes are because of the company’s implementation choices for its next-gen process tech. Intel’s 10-nm process is rather unusual among cutting-edge lithography because of the company’s decision to forgo EUV insertion entirely in favor of multi-patterning with traditional 193-nm deep ultraviolet light sources.
Although Intel has said in the past that it was using self-aligned quad patterning as part of 10-nm production, Krzanich offered the eyebrow-raising prospect that the company has to employ as many as five or six multi-patterning steps to create certain 10-nm features in response to one analyst question.
Krzanich didn’t say whether those figures were merely examples of multi-patterning in general or specific examples of steps needed to produce Intel 10-nm chips, but the sheer number of steps inolved in multi-patterning on that scale could be a major factor in the yield problems that Intel is experiencing. As GlobalFoundries put it to me during our foundry tour earlier this year, every interaction a silicon wafer has with lithography tools increases the chance of a defect, and multi-patterning involves a lot of interactions with those tools as a wafer is shepherded to completion.
In contrast, GlobalFoundries notes that EUV not only allows for more efficient usage of foundry capacity, it also reduces the number of times equipment needs to interact with the wafer. EUV users still face significant challenges of their own regarding yields and defect detection in the masks that will be used to guide light to wafers, but the fact that it broadly reduces the number of steps involved in putting chips on silicon may have positive implications for yields and productivity, all else being equal.
Intel won’t enjoy any of the potential benefits of EUV before its 7-nm process goes into production. Krzanich told analysts that 10-nm will be the last Intel lithography node without EUV insertion, but the company hasn’t announced a timeline for insertion of those tools or when it’ll begin high-volume 7-nm manufacturing. Given the lengthy continued work that 10-nm appears to need before it enters high-volume manufacturing, it’s not at all clear when Intel 7-nm chips will first see the light of day.
The toil on 10-nm appears necessary for transitions to future nodes, as well. Krzanich told analysts that the company plans to stay the course on 10-nm so that it can glean the knowledge it needs to effectively make 7-nm silicon, rather than throw away the work it’s already invested in 10-nm production and jump straight to the next process node.
Even with the delays involved in ironing out yield issues, the 10-nm silicon slated to arrive in 2019 will still be of the first-generation variety—not the “10-nm+” transistors that seem poised to finally outperform those available from the ultimate n-plus variants of the evergreen 14-nm process. The CEO told analysts that the improvements going into 10-nm at the moment are mostly focused on yield improvements for the base process, not the performance gains offered by a 10-nm+ variant.
To EUV or not to EUV
Going by the publicly-available information, GlobalFoundries’, TSMC’s, and Samsung’s 7-nm processes will all have feature sizes and density broadly similar to Intel’s 10-nm proccess, and they’ll all use EUV tools for critical layers at some point within their life cycles. GlobalFoundries will use EUV for contacts and vias first before laying down critical features with that exotic radiation, while Samsung will go whole-hog on critical features from the get-go.
TSMC is using a more Intel-like approach for its initial 7-nm technology, called N7. According to information gathered by WikiChip, TSMC’s initial 7-nm process still uses self-aligned quad-patterning with a 193-nm light source. Anandtech had an opportunity to go deep on TSMC’s next-generation technologies, and it reports that the company is saving EUV for a next-generation process called N7+.
N7+ will introduce EUV at critical layers, and unlike GlobalFoundries’ 7LP, that transition will not be transparent to the companies using it. Anandtech says that some redesign work will be required for N7+, as it will not only offer performance improvements but also density improvements—and require routing changes—compared to N7.
In fairness, Samsung and GlobalFoundries’ 7-nm processes are by most accounts not set to ramp until later this year, so it’s too early to say whether those companies will experience their own yield headaches from their next-generation lithography tech. In its latest earnings call, however, TSMC claims that its N7 process has already been used to fabricate 18 separate products with “good yield and performance,” and that it is already using that process for volume production. Even allowing for some margin in the meaning of “good yield,” that fact would suggest TSMC has overcome the challenges of laying down the infinitesimal features of its 7-nm parts even without EUV tools.
If TSMC’s description of the state of its process tech is true, and its first 7-nm chips begin appearing in retail products at any point this year, it would likely mark the end of Intel’s long-touted process advantage over foundry competitors. Broadly speaking, TSMC N7 has a contacted poly pitch, minimum metal pitch, and SRAM bitcell density similar to Intel’s 10-nm process, according to Wikichip. GlobalFoundries’ 7-nm process is similarly dense. Those two developments would give Intel competitors like AMD, Nvidia, and perhaps even Apple a much more even playing field with Intel’s fabs as they implement their next designs in silicon.
What’s worse for Intel is that its pure-play foundry competition is not standing still. TSMC already says that it’s seeing similar yields and “tighter distributions of electrical parameters” from its N7+ follow-on with EUV, that it has customers asking to tape out products on N7+ in the second half of 2018, and that volume production of N7+ chips will begin in 2019. If N7+ holds to its claimed 10% to 20% density improvements, a pure-play foundry could even have an edge on Intel’s fabs next year—an event that would be unprecedented in 21st-century semiconductor production, to my knowledge.
Lakes, lakes all around
In the near term, Intel says that it will continue to refine its 14-nm process and deliver new chips built on the technology. The company touts the fact that it’s already delivered higher-performance transistors as it’s refined 14-nm through its 14-nm+ and 14-nm++ optimizations, and it’s undeniable that the work on those improvements has paid off handsomely in chip families like Kaby Lake Refresh and Coffee Lake.
As a result, it’s a no-brainer that Intel will continue to introduce new chip families built on 14-nm until it gets 10-nm yields in hand. Krzanich revealed that Intel will introduce a new processor family called Whiskey Lake for client PCs later this year. Whiskey Lake could include a long-rumored eight-core CPU for its mainstream sockets. The company also plans to introduce a new family of server parts called Cascade Lake for the data center in the same time frame.
It’s undeniable that Intel still makes many of the highest-performance chips in the industry, and the company seems poised to bring much-needed new blood into markets like graphics processing units. Its earnings call also made it clear that the company is still exploring innovative new methods of heterogeneous chip packaging that would allow it to build different functional blocks of chips on different processes and bring them together using its EMIB technology.
Until Intel has a next-generation process to build its very-highest-performance next-generation chips on, however, it seems as though it’ll be hobbled in its ability to introduce denser chips and new microarchitectures just as the rest of the semiconductor industry is making big strides. The next couple of years could be some of the most interesting yet in chip production as companies chase the very limits of physics, and Intel seems to have its work cut out for it if it wants to stay ahead of the game—presuming the game is still Intel’s to lose.